The pair of MEM_SIZE/ADDR registers get programmed in sequence with the size/addr of each buffer. aka clip_halfz range of -8.0 to 8.0 range of -512.0 to 512.0 RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS render targets - 1 Pitch (actually, appears to be pitch in bytes, so really is a stride) in GMEM, so pitch of the current tile. offset into GMEM (or system memory address in bypass mode) actually, appears to be pitch in bytes, so really is a stride Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER seems to be always set to 0x00000000 DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie bin_w * bin_h / 1024 (possible rounded up to multiple of something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes 80.. so maybe it needs to be multiple of 8?? Pitch of depth buffer or combined depth+stencil buffer in z24s8 cases. seems to be always set to 0x00000000 Base address for stencil when not using interleaved depth/stencil pitch of stencil buffer when not using interleaved depth/stencil seems to be set to 0x00000002 during binning pass X/Y offset of current bin seems to be where firmware writes BIN_DATA_ADDR from CP_SET_BIN_DATA packet.. probably should be called PC_BIN_BASE (just using name from yamato for now) probably should be PC_BIN_SIZE SIZE is current pipe width * height (in tiles) N is some sort of slot # between 0..(SIZE-1). In case multiple tiles use same pipe, each tile gets unique slot # STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4 (but, in cases where you'd expect 1, the blob driver uses 2, so possibly 0 (no varying) or minimum of 2) indexed by dimension indexed by dimension, global_size / local_size TOTALATTRTOVS is # of attributes to vertex shader, in register slots (ie. vec4+vec3 -> 7) STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid MAXSTORAGE could be # of attributes/vbo's SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1 From register spec: SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object start offset in on chip RAM, 128bit aligned The full/half register footprint is in units of four components, so if r0.x is used, that counts as all of r0.[xyzw] as used. There are separate full/half register footprint values as the full and half registers are independent (not overlapping). Presumably the thread scheduler hardware allocates the full/half register names from the actual physical register file and handles the register renaming. From regspec: SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits. If bit31 is 1, it means overflow or any long shader. These seem to be offsets for storage of the varyings. Always seems to start from 8, possibly loc 0 and 4 are for gl_Position and gl_PointSize? SP_VS_OBJ_START_REG contains pointer to the vertex shader program, immediately followed by the binning shader program (although I guess that is probably just re-using the same gpu buffer) The full/half register footprint is in units of four components, so if r0.x is used, that counts as all of r0.[xyzw] as used. There are separate full/half register footprint values as the full and half registers are independent (not overlapping). Presumably the thread scheduler hardware allocates the full/half register names from the actual physical register file and handles the register renaming. From regspec: SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits. If bit31 is 1, it means overflow or any long shader. SP_FS_OBJ_START_REG contains pointer to fragment shader program seems to be one bit per scalar, '1' for flat, '0' for smooth seems to be one bit per scalar, '1' for flat, '0' for smooth render targets - 1 Configures the mapping between VSC_PIPE buffer and bin, X/Y specify the bin index in the horiz/vert direction (0,0 is upper left, 0,1 is leftmost bin on second row, and so on). W/H specify the number of bins assigned to this VSC_PIPE in the horiz/vert dimension. seems to be set to 0x00000001 during binning pass seems to be always set to 0x00000001 seems to be always set to 0x00000001 seems to be always set to 0x00000001 seems to be always set to 0x00000003 seems to be always set to 0x00000001 Texture sampler dwords Texture constant dwords INDX is index of texture address(es) in MIPMAP state block Pitch in bytes (so actually stride) SWAP bit is set for BGRA instead of RGBA